iosr-JVSP   Volume-10 ~ Issue-5 ~ Sep. - Oct. 2020

ABSTRACT: This paper presents novel quadruple cross-coupled memory cell designs, namely Proposed cell (BQCCM10T cell), with complete protection against single event upsets and double-node upsets. The proposed cell BQCCM10T consists of four cross-coupled input-split inverters and a buffer.Memory cell circuits are more sensitive to external radiation phenomena that are likely to cause the occurrence of soft errors SEU & DNU. Therefore, the tolerance of the circuit to the soft errors is a stern requirement in memory cell circuit designs. Since the traditional error-tolerant methods result in significant cost fines in terms of power, area, and performance, the development of low-cost hardened designs for storage cells(such as latches and memories)is of increasing importance. The Proposed cell achieves complete SEU and DNU tolerance through feedback and buffering mechanisms among its internal nodes.The proposed BQCCM10T cell has high robustness and high Read Access time and Write Access Time. With the help of T-Spice, simulation results of several SRAM cells and the BQCCM10T cell are compared.Hence the proposed cell BQCCM10T is used for highly terrestrial reliable low voltage applications..

Keywords: Single Event Upset, Double Node Upset, Memory Cell, Soft Error, Quadruple Cross coupled memory cell.

[1]. Aibin Yan, Jun Zhou, Yuanjie Hu, Jie Cui, Zhengfeng Huang, Patrick Girard, and Xiaoqing Wen, ―Novel Quadruple Cross-Coupled Memory Cell Designs with Protection against Single Event Upsets and Double-Node Upsets,‖ in IEEE Access 2017 Citation information: DOI 10.1109/ACCESS.2019.2958109.
[2]. Y. Shiyanovskii, A. Rajendran, and C. Papachristou, ―A Low Power Memory Cell Design for SEU Protection against Radiation Effects,‖ in Proc. Conf. Adaptive Hardware Syst., Erlangen, Germany, 2012, pp. 288-295.
[3]. D. Lin et al., ―A Novel Highly Reliable and Low-Power Radiation Hardened SRAM Bit-cell Design,‖ IEICE Electron. Express, vol. 15, no. 3, pp. 1-8, Feb. 2018, DOI: org/10.1587/elex.15.20171129.
[4]. C. Qi, L. Xiao, T. Wang, J. Li, and L. Li, ―A Highly Reliable Memory Cell Design Combined with Layout-Level Approach to Tolerant Single-Event Upsets,‖ IEEE Trans. Device Mater. Reliab., vol. 16, no. 3, pp. 388-395, Jul. 2016, DOI: 10.1109/TDMR.2016.2593590.
[5]. ] C. Hu, S. Yue, and S. Lu, ―Design of A Novel 12T Radiation Hardened Memory Cell Tolerant to Single Event Upsets (SEU),‖ in Proc. IEEE 2nd Int. Conf. Integr. Circuits Microsyst, Nanjing, China, Jan. 2017, pp. 182-185

ABSTRACT: Today the synthetic speech of highest quality, generated by existing speech synthesis systems are not close to actual human speech. As the number of applications for synthetic speech increases, the naturalness and the intangibility of synthetic speech will become an important factor in determining its use. This paper presents a comparative study on investigating the naturalness and the intelligibility of the newly proposed Auto Regressive Moving Average (ARMA) based speech synthesis method for female voice. The synthesized speech was analyzed based on subjective and objective measure. The subjective measures, signal-to-noise ratio (SNR), peak signal-to-noise ratio (PSNR) and.......

Keywords: Auto Regressive Moving Average (ARMA), Speech intelligibility; Naturalness; signal-to-noise ratio (SNR); peak signal-to-noise ratio (PSNR) and mean square error (MSE); Diagnostic Rhyme Test

[1]. Vaseghi, S., V., Multimedia Signal Processing: Theory and Applications in Speech, Music and communications. John Wiley and Sons Ltd, 2007.
[2]. Keller. E., Baily, G., Monaghan, A., Huckvale, M., Improvements in Speech synthesis, COST 258: The Naturalness of Synthetic Speech, John Wiley & Sons, LTD .
[3]. Taylor, P., Text to Speech Synthesis, Cambridge University Press, 2009.
[4]. C.V. Botinh˜ao, Intelligibility enhancement of synthetic speech in noise Doctor of Philosophy thesis, Institute for Language, Cognition and Computation School of Informatics University. of Edinburgh. 2013
[5]. Wang, M., Speech Analysis And Synthesis Based On ARMA Lattice Model, Master's Thesis, University of Windor, 2003

ABSTRACT: In this paper, a new approach to assess the skew angle for scanned/printed documents and historical document images has been proposed. This is substantial for an automatic document processing system (as text and image segmentation) to avert errors in auxiliary stages. The proposed tactic is based on the statistical analysis of the slope of the connected lines in the document. The proposed technique detects skew and corrects it by initial letter (X1, Y1+200) from left margin of the resized (800X800) image and (X1+200, Y1) from top, (X1, Y1+200) from bottom margin. Final letter (X2, Y2-200) and (X2-200, Y2) were chosen from right and bottom margins of the same image. The skew angle estimation is done for standard skewed dataset and effective correction of the same is performed with minimum errors..

Keywords: Printed text, Multiple Skew, Skew Detection and Correction

[1]. DarkoBrodic, Carlos A B Mello : An Approach to Skew Detection of Printed Documents : Journal of Universal Computer Science Vol 20, no 4 (2014), pp 488-506
[2]. Babu, D R., Kumat. P M., : Skew angle estimation and correction of handwritten, textual and large areas of non-textual document images: A noval approach. International conference on image processing, computer vision and pattern recognition. pp 510-515, (2006)
[3]. N .Nandini, K. Srikanta Murthy, and G. Hemantha Kumar, "Estimation of skew Angle in binary document images using Hough transform," Journal of World Academy of Science, Engineering and Technology, vol. 32, pp. 50-55, August 2008.
[4]. A.Amin and S.Fischer, "A document skew detection method using the Hough transform," Pattern Analysis and Applications, vol. 3, pp.243-253, September 2000
[5]. KL Banumathi and AP Jagadeesh Chandra, "A new algorithm for Skew Detection and Correction of Historical Kannada Documents", International Conference on Multimedia Processing Communication and Information Technology MPCIT– 2018, 8th and 9th June, 2018

ABSTRACT: In this research, the Dynamic Element Matching Technique (DEM) algorithm is used, known as Partial Binary Tree Network (PBTN), been proposed from previous research that aims to push the boundaries from 8-bit to 10-bit. PBTN is used because it has a lower complexity circuit and fewer glitches produced at the output signal. Besides, in this research, the Current Controlled Current Source (CCCS) used to magnify the output in previous research is replaced with an operational amplifier (op-amp). The 8-bit 1-MSB achieved a power consumption of 16.7 mW, much lower compared to the previous research. For 10-Bit 1-MSB, the circuit achieved DNL of -0.535378495 LSB, INL of 0.955382 LSB, with a power consumption of 66.31 mW.

Keywords: Partial Binary Tree Network, Dynamic Element Matching, current steering DAC, INL, DNL,10-BIT 1-MSB

[1]. Robert Gregoire, B. & Moon, U.K. Reducing the effects of component mismatch by using relative size information. Proceedingof the IEEE International Symposiumon Circuits and Systems. 2008;512-515.
[2]. Mustaffa, M. T., Lim Y. C., Teh C. Y. Current Steering Digital Analog Converter with Partial Binary Tree Network (PBTN). Indonesian Journal of Electrical Engineering and Computer Science. 2017;5(3):643-649.
[3]. William Yeap, K.S.& Mustaffa, M. T. A 0.13-um 6 to 8-bit PBTN DEM Current Steering DAC. IOSR Journal of VLSI and Signal Processing.2019;9(5):1-10.
[4]. Myderrizi, I. &Zeki, A. Current-Steering Digital-to-Analog Converters: Functional Specifications, Design Basics, and Behavioral Modeling. Antennas and Propagation Magazine, IEEE.2010; 52:197-208.
[5]. Galton, I. Why Dynamic-Element-Matching DACs Work. IEEE Transactions on Circuits and Systems II: Express Briefs. 2010; 57:69-74.

ABSTRACT: Paper presents a new design approach of voltage-controlled ring oscillator for PLL based applications in a communication system for low voltage and power range. This approach reports a 1.8 GHz to 2.8 GHz five stages VCO design using current starved method for CMOS technology. Paper also reports comparative analysis of five stages VCO with three stages VCO. Five stage design analysis shows 3.07 μW power consumption for 22 nm @ 0.4 GHz to 26.04 GHz and three stages design represents 15 mW for 180 nm @15 MHz to 5 GHz.

Keywords: CMOS, VCO, PLL, FFT, PMOS, NMOS

[1]. Bodhisatwa Sadhu,, Mark A. Ferriss, Arun S. Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes- Garcia, Benjamin D. Parker, Aydin Babakhani, Scott Reynolds, Xin Li, Larry Pileggi, Ramesh Harjani, José A. Tierno, and Daniel Friedman, ―A Linearized, ―Low-Phase-Noise VCO-Based 25-GHz PLL With Autonomic Biasing‖, IEEE Journal of solid-state circuits, Vol. 48, NO. 5, May 2013, pp-1138-1148.
[2]. A. Willig, ―Recent and emerging topics in wireless industrial communications: A selection,‖ IEEE Trans. Ind. Informat., Vol. 4, no. 2, May 2008, pp. 102–124.
[3]. Sushil Kumar and Gurjit Kaur, ―Design and Performance Analysis of nine stages CMOS based ring Oscillator‖, International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.3, June 2012.
[4]. Sajotra Deepak, Dhariwal Sandeep and Mishra Ravi Shankar, ―Comparative Analysis of Voltage Controlled Oscillator using CMOS‖, Indian Journal of Science and Technology, Vol 9(14), April 2016..