iosr-JVSP   Volume-5 ~ Issue-1 ~ Jan-Feb 2015

ABSTRACT: In recent years, the accurate computer aided diagnosis of the cardiovascular diseases is gaining momentum. In addition to accuracy, non-invasiveness of the measurement techniques has become the need of the hour. Impedance cardiography is one such method which has become a synonym for indirect assessment of monitoring the stroke volume, cardiac output and other hemodynamic parameters by monitoring the blood volume changes of the body. Changes occurring in the blood volume within a certain body segment due to various physiological processes are captured in terms of the impedance variations of that segment. But this method is affected by electrical noise such as power line hum and motion and respiratory artifacts due to movement of the subject while acquiring the bioimpedance signal. This can cause errors in the automatic extraction of the characteristic points for estimation the hemodynamic parameters. This paper presents two algorithms for baseline wander removal from the bioimpedance waveform obtained at the radial pulse of the left hand, one based on wavelet packet decomposition and the other based on the Kalman filter. The impedance signals have been acquired by using the peripheral pulse analyzer. The results for the wavelet packet decomposition are found to be better than that of the Kalman filter.

Keywords: Bioimpedance, Artifact, Baseline wander, Energy, Impedance cardiography, Radial, Wavelet packet transform, Kalman filter

[1] Vinod KP, Prem CP, Nitin JB, and Subramanyan LR. "Adaptive Filtering for Suppression of Respiratory Artifact in Impedance Cardiography", 33rd Annual International Conference of the IEEE EMBS: Boston, Massachusetts USA; August 30-September 3; 2011.
[2] R. P. Patterson, "Fundamental of impedance cardiography," IEEE Eng. Med. Biol. Mag., vol. 8, pp. 35-38, Mar. 1989.
[3] B. E. Hurwitz et al, "Coherent ensemble averaging techniques for impedance cardiography," in Proc.3rd Annu. IEEE Symp. Comp. Based Med. Syst., June 1988.
[4] C. R. Meyer and H. N. Keiser, "Electrocardiogram baseline noise estimation and removal using cubic splines and statespace computation techniques," Computers and Biomedical Research, vol. 10, no. 5, pp. 459–470, 1977.
[5] L. Sornmo, "Time-varying filtering for removal of baseline wander in exercise ECGs," in Proceedings of Computers in Cardiology, pp. 145–148, Venice, Italy, September 1991.
[6] J. A. Van Alste and T. S. Schilder, "Removal of base-line wander and power-line interference from the ECG by an efficient FIR filter with a reduced number of taps," IEEE Transactions on Biomedical Engineering, vol. 32, no. 12, pp. 1052–1060, 1985.

ABSTRACT: Error Correction Codes (ECCs) are commonly used to protect memories from soft errors. As technology scales, Multiple Cell Upsets (MCUs) become more common and affect a larger number of cells. To prevent the occurrence of MCUs several error correction codes (ECCs) are used, but the main problem is that they require complex encoder and decoder architecture and higher delay overheads. The decimal matrix code (DMC) minimizes the area and delay overheads compared to the existing codes such as hamming, RS codes and also improves the memory reliability by enhancing the error correction capability. In this paper, novel decimal matrix code (DMC) based on divide-symbol is proposed to enhance memory reliability with lower delay overhead. The proposed DMC utilizes decimal algorithm to obtain the maximum error detection capability. Moreover, the encoder-reuse technique (ERT) is proposed to minimize the area overhead of extra circuits without disturbing the whole encoding and decoding processes. ERT uses DMC encoder itself to be part of the decoder.

Keywords: Error correction codes, multiple cell upsets, decimal matrix code, encoder reuse technique.

[1]. R. C. Baumann, "Radiation-induced soft errors in advanced semiconductor technologies," IEEE Trans. Device Mater. Reliab., Vol. 5, no. 3, pp. 301–316, 2005.
[2]. M. Zhang and N. R. Shanbhag, "Dual-sampling skewed CMOS design for soft-error tolerance," IEEE Trans. Circuits Syst. II, Exp. Briefs, Vol. 53, no. 12, pp. 1461–1465, Dec. 2006.

ABSTRACT: Clock signal have been a great source of power dissipation in synchronous circuits because of high frequency and load. So , by using clock gating one can save power by reducing unnecessary switching activity inside the gated module. Here four gating methods are discussed and their power dissipation is compared. The most popular is synthesis-based, deriving clock enabling signals based on the logic of the underlying system. It unfortunately leaves the majority of the clock pulses driving the flip flops (FFs) redundant. A data driven method stops most of those and yields higher power savings, but its implementation is complex and application dependent. A third method called auto gated FFs (AGFF) is simple but yields relatively small power savings. Another novel method called Look Ahead Clock Gating (LACG) is presented, which combines all the three.It avoids the tight timing constraints of AGFF and data driven by allotting a full clock cycle for the computation of the enabling signals and their propagation.

Keywords: AGFF,LACG, Flip Flops, Clock Gating

[1]. Shmuel wimer and arye albhari,"A look ahead clock gating based on autogated flip flop",IEEE , vol.61,no.5, may 2014.
[2]. Jagrit kathuria ,M.Ayoubkhan and Arti noor ,"A review of clock gating techniques"MIT international journal of electronics and communication engineering,vol 1 no 2, aug 2011.
[3]. W.Shen,Y.Cai,X.HongandJ.Hu,"Activity register placement aware gated clock network design", in proc,ISPD 2008.
[4]. S.Wimer and I.Koren,"The optimal fanout of clock network for power minimisation by adaptive gating",IEEE trans.VLSI syst.,vol 20 no.10,oct 2012.
[5]. M.S.Hosny and W. Yuejian, "Low power clocking strategies in deep submicron technologies," in Proc. IEEE Int. Conf. Integr. Circuit Design Technol., ICICDT pp. 143–146 , 2008.

ABSTRACT: Memory can be formed with the integration of large number of basic storing element called cells. SRAM cell is one of the basic storing unit of volatile semiconductor memory that stores binary logic '1' or '0' bit. Modified read and write circuits were proposed in this paper to address incorrect read and write operations in conventional 6T SRAM cell design available in open literature. Design of a new highly reliable 6T SRAM cell design is proposed with reliable read, write operations and negative bit line voltage (NBLV). Simulations are carried out using MENTOR GRAPHICS.

Keywords: Memory, Read, Write, SRAM, NBLV.

[1]. The Impact of Total Ionizing Dose on Unhardened SRAM Cell Margins IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 55, NO. 6, DECEMBER 2008
[2]. Masood Qazi, Mahmut E. Sinangil, and Anantha P. Chandrakasan, "Challenges and Directions for Low-Voltage SRAM", Copublished by the IEEE CS and the IEEE CASS 0740-7475/11/$26.00 2011.
[3]. Kaushik Roy, Sharat C. Prasad, "Low-Power CMOS VLSI Design", a John Wiley & Sons, 02-Feb-2009.
[4]. Jan M. Rabaey, Anantha P. Chandrakasan, Borivoje Nikolic, "Digital integrated circuits: a design perspective", Pearson Education, 2003.
[5]. Sung-Mo Kang, Yusuf Leblebici, "CMOS Digital Integrated Circuits: Analysis and Design", Tata McGraw-Hill Education.
[6]. Neil H. E. Weste, David Money Harris, "CMOS VLSI Design: A Circuits and Systems Perspective", Addison Wesley, 2011..

ABSTRACT: This paper focuses mainly on dynamic power dissipations at different temperature for both read and write operations of 12T SRAM. In the proposed 12T structure virtual vdd concept is employed because of this leakage current will reduce. Hence reduction in leakage current causes reduction in dynamic power. Power dissipation of the proposed SRAM cell have been determined and compared to those of some other existing memory cells. Proposed cell is a short channel BSIM4 model. It is observed that power dissipation of 12T SRAM for read operation at 40̊̊ is 44.7nw and for write operation it is 38.79nw. The proposed SRAM cell dissipates less power. Simulation has been done in Tanner-13 EDA tool for 50nm.

Keywords: BSIM4 model, Dynamic power, Low power SRAM, Virtual vdd.

[1]. P. Upadhyay, Nidhi Agarwal, R. Kar,1D. Mandal, S. P. Ghoshal , "Power and Stability Analysis of a Proposed 12T MTCMOS SRAM Cell for Low Power Devices"(2014).
[2]. P. Upadhyay, Sarthak Ghosh, R. Kar, D. Mandal, S. P. Ghoshal, "Low Static and Dynamic Power MTCMOS Based 12T SRAM Cell for High Speed Memory System", 2014 11th International joint Conference on Computer science & software engineering (JCSSE)
[3]. Do Anh-Tuan, Jeremy Yung Shern Low, Joshua Yung Lih Low, Zhi-Hui Kong, Xiaoliang Tan, and Kiat-Seng Yeo, "An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 6, (JUNE 2011)
[4]. Nam Sung Kim, Stark C. Draper, Shi-Ting Zhou, Sumeet Katariya, Hamid Reza Ghasemi, and Taejoon Park, "Analyzing the Impact of Joint Optimization of Cell Size, Redundancy, and ECC on Low-Voltage SRAM Array Total Area", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 12, DECEMBER 2012.

ABSTRACT: This paper out mark the application of image processing techniques for automatic detection of eye diseases called Macular Ischemia. Large percentages of people suffer from various eye diseases in semi urban and rural areas in world over. Image processing techniques helps in diagnosing various eye diseases. Macular diseases have a great variety of textures and shapes and at times they are hard to be recognised and identified even by doctors. Thus we are trying to develop and optimize such a system based on intelligent image classification/ recognition algorithms. The system offers speed, accuracy, consistence and a high confidence coefficient in results interpreting.

Keywords: Macular Ischemia, diagnosis, textures, consistence Keywords: consistence, diagnosis ,Macular Ischemia, optimize, textures.

[1]. ManjulaSri Rayudu, Vaibhav Jain, MM.Rao Kunda,,"Review of Image Processing Techniques for Automatic Detection of Eye Diseases", ©2012 IEEE
[2]. M. Usman Akram, Sundus Mujtaba*, Anam Tariq, "Automated Drusen Segmentation in Fundus Images For Diagnosing Age related Macular Degeneration", ©2013 IEEE
[3]. M. Luculescu, "Macular Diseases Recognition Using Neural Networks",The First National Conference of Medical Engineering –COPTOMIM 2006, Braşov, 2006, pp. 155-158.
[4]. M. Luculescu, Researches on Biological Human Visual Structures Concerning the Diagnosis of Macular Diseases, PhD Thesis, 2007.
[5]. M. C. Luculescu1, S. Lache1 "Using Artificial Neural Networks in a ComputerAided Diagnosis System for Macular Diseases",@2008IEEE.

ABSTRACT: Video compression has two major issues to be handled, one is video compression rate and other one is quality. There is always a trade-off between speed and quality. Full search block matching algorithm (FSBMA) is most popular motion estimation algorithm. But high computational complexity is the major challenge of FSBM. This makes FSBM to be very difficult to use for real time video processing with the low power batteries. Other algorithm gives better speed on the expense of quality of video. The proposed algorithm i.e. modified full search block matching algorithm (MFSBMA) reduces the computational complexity by keeping the PSNR same as of FSBMA. MFSBMA skips the SAD calculations for a current background macroblock and it does SAD calculations for foreground current microblock. This method reduces SAD calculations drastically. This work presents apipelined architecture forMFSBMA which can work on real time HDTV video processing. The proposed algorithm reduces computational complexity by 50% keeping PSNR same with the full search algorithm.

Keywords: Full Search Block Matching algorithm, Block matching algorithm, Motion Estimation, H.264/AVC, motion vector.

[1]. International Telecommunication Union Telecommunication (ITU-T). Draft text of draft international standard for advance video coding. Recommendation H.264 (draft), 2003.
[2]. ITU-T Recommendation H.264 & ISO/IEC 14496-10 (MPEG-4) AVC. Advance video coding for generic audiovisual services. (Version 1: 2003, version 2: 2004, version 3: 2005).
[3]. Seung-Man Pyen, Kyeong-Yuk Min, Jong-Wha Chong," An Efficient Hardware Architecture for Full-Search Variable Block Size Motion Estimation in H.264/AVC," International Symposium on Visual Computing-2006 , pp. 554-563.
[4]. R. Li, B. Zeng, and M. L. Liou, "A new three-step search algorithm for block motion estimation," IEEE Trans. Circuits Syst. VideoTechnol., vol. 4, pp. 438442, Aug.1994.
[5]. L. M. Po and W. C. Ma, "A novel four-step search algorithm for fast block motion estimation,"IEEE Trans. Circuits Syst. Video Technol., vol. 6, pp. 313317, June 1996.

ABSTRACT: Built-in self test techniques constitute a class of schemes that provide the capability of performing at-speed testing with high fault coverage hence; they constitute an attractive solution to the problem of testing VLSI devices. Concurrent BIST schemes perform testing during the circuit normal operation without imposing a need to set the circuit offline to perform the test; therefore they can circumvent problems appearing in offline BIST techniques. In this brief, a novel input vector monitoring concurrent BIST architecture has been presented, based on the use of a SRAM-cell like register for storing the information of whether an input vector has appeared or not during normal operation. The evaluation criteria for this class of schemes are the hardware overhead and the CTL, i.e., the time required for the test to complete, while the circuit operates normally. The simulation results shown to be more efficient than previously proposed Concurrent BIST techniques in terms of hardware overhead and CTL.

[1] Dongkyu Youn, Taehyung Kim, Sungju Park, "A microcode-based memory BISTimplementing modified March algorithm," Asian Test Symposium, 2001. Proceedings. 10th, 2001, pp. 391-395
[2] Hong Tsai, and Cheng-Wen Wu, "Processor-programmable memory BIST for bus-connected embedded memories," Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific , 2001, pp. 325 -330
[3] Ioannis Voyiatzis and Costas Efstathiou "Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells "IEEE transaction on VLSI system vol no: 22.
[4] Ioannis Voyiatzis, Member, IEEE, Antonis Paschalis, Member, IEEE,Dimitris Gizopoulos, Senior Member, IEEE, Constantin Halatsis,Frosso S. Makri, and Miltiadis Hatzimihail, Student Member, IEEE "An Input Vector Monitoring Concurrent BIST Architecture Based on a Precomputed Test Set" IEEE transactions on computers, vol. 57, no. 8.

ABSTRACT: RC4 Stream cipher is well known for its simplicity and ease to develop in software. But here, in the proposed design we have heighlighted the modified hardware implémentation of RC4. As RC4 is the most popular stream cipher. The proposed design performs reading and swapping simultaneously in one clock cycle. The proposed design also highlights the adder part which enhances the architecture speed. As this design uses fast Carry Look Ahead Adder as the adder logic. RC4 uses a variable length key from 1 to256 bytes to initialize a256-byte array. The array is used for subsequent generation of pseudo-random bytes and then generates a pseudorandom stream, which is XORed with the plaintext/cipher text to give the cipher text/plaintext. The RC4 stream cipher works in two phases. The key setup phase and the pseudorandom key stream generator phase. Both phases must be performed for every new key. The RC4 algorithm will be implemented by FPGA using VHDL software platform.

Keywords: CLA, Clock, FPGA, KRAM, RC4,SRAM, Throughput

[1]. One Byte per Clock: A Novel RC4 Hardware Sourav Sen Gupta1, Koushik Sinha2, Subhamoy Maitra1, and Bhabani P. Sinha1 1 Indian Statistical Institute, 203 B T Road, Kolkata 700 108, India 2 Honeywell Technology Solutions Lab, Bangalore 560 076, India.
[2]. P.kitsos, G. Kostopoulos, N. Sklavos and O.Koufopavlou "IEEE Std 802.11. IEEE Standard:Hardware implementation of the RC4 stream cipher".
[3]. The Fastest Carry Lookahead Adder Yu-Ting Pai And Yu-Kumg Chen Department of Electronic Engineering Huafan University .
[4]. Design and analysis of 16-bit Full Adder using Spartan-3 FPGA Rongali Aneel Kumar, B.N. Srinivasa Rao, R. Prasad Rao Avanthi Institute of Engineering and Technology, Visakhapatnam.
[5]. Fluhrer, I. Mantin, Shamir. "Weaknesses in the key scheduling algorithm of RC4 ". In Proc. 8ih Workshop on Selected Areas in Cryptography, LNCS 2259. Springer-Verlag, 2001. pp. 231-237.