iosr-JVSP   Volume-6 ~ Issue-3 ~ May-June 2016

ABSTRACT: This paper focuses on the development of 80nm channel length of high-k (TiO2) n-channel (NMOS) and p-channel (PMOS) enhancement mode MOSFETs which emerged due to replacement of SiO2 by high-k (TiO2) MOSFETS, as there were many problems while using SiO2 like high leakage current, short channel and electron tunneling effect.

Keywords: Simulation of the fabrication process was carried out by using Tina Pro Software to obtain more accurate process parameters & the results were then compared with NMOS using SiO2 as gate dielectric.

[1]. Chih Chin Yang, Lan Hui Huang, Bo Shum Chen, Jia Liang Ke, and Chung Lun Tsai National Kaohsiung Marine University, Department of Microelectronics Engineering, Kaohsiung, Taiwan, World Academy of Science, Engineering and Technology, "Inductance Characteristic of Annealed Titanium Dioxide on Silicon Substrate", World Academy of Science, Engineering and Technology, vol. 56, pp. 1-2, 2009.
[2]. Davinder Rathee, Sandeep K Arya, Department of Electronics and Communication Engineering, Guru Jambheshwar University of Science & Technology, Hisar, India, Mukesh Kumar, Department of Electronics Science, Kurukshetra University, Kurukshetra, India, "CMOS Development and Optimization, Scaling Issue and Replacement with High-k Material for Future Microelectronics", International Journal of Computer Applications, vol. 8, no. 5, pp. 10-11, October 2011.

ABSTRACT:The Evolution of Silicon Technology in the Semiconductor Industry is Prevalent . However, as the technology is scaled down to nanometer regime, there is susequent degradation in MOSFET Characteristics. In this Paper, Comparative Analysis of Proposed DG MOSFET device with previous Model was done using Highk Dielectric material and conventional Bulk SiO2 to investigate the various performance characteristics like hreshold Voltage, DIBL, Sub-threshold Voltage and Leakage (OFF) current using COGENDA VTCAD Simulator.......

Keywords: Dielectric, High-k, MOSFET, Scaling, SCEs, Leakage, DIBL, SS

[1]. T.Sood, R.Mehra, "Design A Low Power Half Subtractor Using 90 μm CMOS Technology" ,IOSR Journal of VLSI and Signal Processing, Vol2, issue.3, pp.51-56,2013.
[2]. International Technolgy Roadmap for Semiconductors(http://Public.itrs.net/).
[3]. Y.K. Choi, K. Asano, N.Lindert, V. Subramanian, T.J King, J.Bokor, and C.Hu, "Ultrathin-body SOI MOSFET for Deep-Sub-
[4]. Length Micron Era,"IEEE Electron Device letters, Vol 21, No.5, pp.254, 2000.
[5]. K.Uchida, H.Watanabe, a. Kinoshita,J.Koga, T.Numata, and S.I.Takagi, "Experimental study on carrier transport mechanism in

ABSTRACT:This paper is based on pre layout schematic simulations of a proposed design of 2:1 MDCVSL multiplexer circuit that shows improved performance than the existing 2:1 multiplexer circuit. The proposed design shows superiority in terms of power consumption and temperature sustainability when compared with existing 2:1 CMOS multiplexer and comparative analysis on 90nm technology.....

Keywords: Multiplexer, Adiabatic Logic, Low Power, GDI Logic, MDCVSL Logic.

[1]. Meenakshi Mishra, Shyam Akashe "High performance, low power 200 Gb/s 4:1 MUX with TGL in 45 nm technology" Springer, Applied Nanoscience, Vol 4, Issue 3, pp 271-277 Mar 2014
[2]. Ila Gupta, Neha Arora, B.P. Singh, "An Efficient Design of 2:1 Multiplexer and its Application in 1-Bit Full Adder Cell", International Journal of Computer Applications, Volume 40– No.2, pp 31-36, February 2012
[3]. Debika Chaudhuri, Atanu Nag, Sukanta Bose, Suchismita Mitra, Hemanta Ghosh , "Power and Delay Analysis of a 4 to 1 Multiplexer Implemented in different Logic Style" International Journal of Innovative Research in Science, Engineering and Technology, Volume 4, Special Issue 9, pp 118-123, July 2015
[4]. Yashika Thakur, Rajesh Mehra, Anjali Sharma, " CMOS Design of Area and Power Efficient Multiplexer using Tree Topology", International Journal of Computer Applications, Volume 112, No 11, pp 32-36, February 2015.

ABSTRACT: The paper presents a new design for full adder by utilizing the cascade voltage switch logic. Adders are the basic building block for all the functional units of microprocessors and digital signal processors. In the growing era of nanotechnology, it has become necessary to develop methodologies to efficiently reduce the area and power consumption.......

Keywords: Circuit Simulation, CMOSFET Circuits, CVSL, Full Adder.

[1]. Ranjeeta Verma, Rajesh Mehra, "CMOS Based Design Simulation Of Adder /Subtractor Using Different Foundries", International Journal of Science and Engineering, Vol. 2, Issue 1, pp. 22-27, 2013.
[2]. R. Singh, R. Mehra, "Low power TG full adder design using CMOS nano technology", 2nd IEEE International Conference on Parallel Distributed and Grid Computing, Vol. 2, pp. 210-213, Dec 2012.
[3]. A. Sharma, R. Mehra, "Area and Power efficient CMOS Adder design by hybridising PTL and GDI technique", International Journal of Computer Applications, Vol. 6, Issue 5, pp. 15-22.
[4]. Pradeep Kumar, "Existing Full Adders and Their Comparison on The Basis of Simulation Result And to design a improved LPFA (Low Power Full Adder)" , International Journal of Engineering Research and Applications, Vol. 2, Issue 6, pp. 599-606, Nov-Dec 2012.

ABSTRACT: Adder forms the basis of many processing operations making it one of the most important components in ALU design. Improving its performance can enhance the performance of the overall processing system. In this paper a full adder design is presented using GDI technique. The main objective is to get reduced delay and power consumption........

Keywords: GDI, CMOS, full adder, time delay, power consumption.

[1] N. Weste and K. Eshraghian, "Principles of CMOS VLSI Design," Pearson Education, pp. 134-147, 2002.
[2] Etienne Sicard, Sonia Delmas Bendhia, "Basic of CMOS cell design, Tata Mc Graw-Hill, pp. 89-110.
[3] Anjali Sharma and Rajesh Mehra "Area and Power Efficient CMOS adder design by Hybridizing PTL and GDI Technique," International Journal of Computer Applications, Vol. 66, No. 4, pp. 15-22, March 2013.
[4] Anjali Sharma, R. Singh and Rajesh Mehra "Low power TG full adder design using CMOS nano technology," Parallel Distributed and Grid Computing (PDGC), 2nd IEEE International Conference, pp. 6-8, December 2012.
[5] R. Singh, R. Mehra, "Low power TG full adder design using CMOS nano technology", 2nd IEEE International Conference on Parallel Distributed and Grid Computing, pp. 210-213, Dec 2012.

ABSTRACT: This paper presents an efficient design and implementation of low area, high speed Adaptive filter based on Distributed Arithmetic (DA) Scheme. An enhanced NLMS algorithm has been proposed for the adaptive noise cancellation filter design. The computation speed of the proposed NLMS system is relatively high due to preallocation of memory for variables in enhanced Normalized LMS algorithm.The proposed design is successfully implemented using Matlab Code and Xilinx ISE Design Suit on Spartan 3 based XC 35400 and Spartan 3E based Xc3500e FPGA device........

Keywords: Adaptive Filters, Distributed Arithmetic, FPGA, NLMS Algorithm, Noise Cancelation.

[1] RuiGuoAnd Linda S. De Brunner ―Two High- Performance Adaptive Filter Implementation Schemes Using Distributed Arithmetic‖ IEEE Transactions On Circuits And Systems—II: Express Briefs, Vol. 58, No. 9, Pp. 600-604, September 2011.
[2] S. Haykin, ―Adaptive Filter Theory‖, Pearson Education Asia, 3rd Edition, pp. 324-414.
[3] Srishtee Chaudhary and Rajesh Mehra, ―FPGA Based Adaptive Filter Design Using Least PTH-Norm Technique‖, International Journal of Soft Computing and Engineering (IJSCE), ISSN: 2231-2307, Vol. 3, No. 2, pp. 208-211, May 2013.

ABSTRACT: Barrel Shifter plays an important role in optimizing the RISC processor and used for rotating and shifting the data either in left or right direction. This shifter is useful in many signal processing ICs. The arithmetic and logical shifter are itself a type of barrel shifter. The main objective of this paper is to design a fully custom two bit barrel shifter using 2x1 multiplexer with the help of CMOS logic and analyse the performance on basis of power consumption, time delay and no of transistors. The tool used to fulfill the purpose is cadence virtuoso using 45nm technology. The power consumption is reduced by 76.37% and time delay by 91.77% in the proposed design.

Keywords: Barrel Shifter, CMOS, MUX, Power consumption, Time delay

[1]. RenukaVerma, Rajesh Mehra, "Area Efficient Layout Design AnalysisOf CMOS Barrel Shifter," International Journal of Scientific Research Engineering & Technology (IJSRET), pp. 84-89, March 2015.
[2]. A Sharma, Rajesh Mehra, "Area and Power Efficient CMOS Adder Design By Hybridizing PTL and GDI Technique," International Journal of Computer Applications, Vol.66, No.4, pp.15-22, March 2013.
[3]. Shilpa Thakur, Rajesh Mehra, "CMOS Design and Single Supply Level Shifter Using 90nm Technology," Conference on Advances in Communication and Control Systems, pp.150-153, 2013.
[4]. R Singh, Rajesh Mehra, "Power Efficient design of Multiplexer using Adiabatic logic," International Journal Of Advances Engineering and Technology, Vol.6, Issue.1, pp.246-254, March 2013.
[5]. Prasad D Khandekar, Dr. Mrs. ShailaSubbaraman, "Low Power 2:1 MUX for Barrel Shifter," International Conference On Emerging Trends In Engineering and Technology,IEEE, pp.404-407, July 2008.

ABSTRACT: Nowadays, we hardly find any field which is not advancing rapidly, modern communication systems are also advancing at a faster rate. So it is mandatory we must design the techniques to evaluate the performance of such modern communication systems like Software Defined Radio (SDR), Cognitive Radio using reconfigurable devices like FPGA. This paper presents the technique for the performance measurement of digital modulation schemes since the digital modulation schemes are superior as compared to analogue modulation schemes............

Keywords: Bit Error Rate (BER), signal to noise ratio (SNR),signal to noise and distortion ratio (SNDR), software defined radio (SDR), field programmable gate array (FPGA).

[1] AmirhosseinAlimohammad and SaeedFouladiFard, "FPGA-Based Bit Error Rate Performance Measurement of Wireless Systems," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, VOL. 22, NO. 7, JULY 2014
[2] FaruqueAhamed, and Frank A. Scarpino, "An Educational Digital Communications Project Using FPGAs to Implement a BPSK Detector," IEEE Trans. on Education, VOL. 48, NO. 1, FEBRUARY 2005
[3] Kaliprasanna Swain & Manoj Kumar Sahoo, "FPGA Implementation of QPSK Modulator Based on Matlab/Xilinx System Generator," International Conference on Recent Innovations in Engineering & Technology, April 2014
[4] Devanshi S. Desai1, Dr. Nagendra P. Gajjar, "Low Bit-rate Modulator Using FPGA," InternationalJournal of Electronics And Communication Engineering & Technology, Vol. 5, Issue 4, April 2014
[5] T. K. Zombade, S. A. Shirsat, "QPSK Modem using FPGA," International Journal of Electronics Communication and Computer Engineering, Volume 5, April, 2014

ABSTRACT:In Digitally Controlled Delay Lines (DCDL) there are different ways to optimize the design of the circuit. DCDLs are used in number of applications such as phase locked loops and delay locked loops. They are used to mainly process the clock signals. These lines produce a programmable delay to the output with respect to the input and also adjust the relative difference between the two signals to produce the reliable data transfer. It is also finds its applications in digital- to-analog converter where time domain resolution is given more importance than the voltage resolution. A digital delay line includes a plurality of delay elements, arranged in sequence having an associated control input.

[1]. Chen P. L, Chung C. C, and Lee C.Y, "A portable digitally controlled oscillator using novel varactors," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 52, no. 5, pp. 233–237, May 2011.
[2]. Chen P. L, Chung C. C, Yang J. N, and Lee C. Y., "A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications," IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1275–1285, Jun. 2012.
[3]. Choi K. H, Shin J. B, Sim J. Y, and Park H. J, "An interpolating digitally controlled oscillator for a wide range all digital PLL," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 9, pp. 2055–2063, Sep. 2009.
[4]. Matano T. M, Takai Y, Takahashi T, Sakito Y, Fujii I, Takaishi Y, Fujisawa H, Kubouchi S, Narui S, Arai M, Morino K, Nakamura M, Miyatake S, Sekiguchi T, and Koyama K, "A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer," IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 762–768, May 2010.

ABSTRACT: This Paper presents an efficient implementation of high speed multiplier using the shift and add method, Radix_2, Radix_4 modified Booth multiplier algorithm. In This paper we compare the working of the three multipliers by implementing each of them separately in FIR filter. The parallel multipliers like radix2 and radix4 modified booth multiplier does the computations using lesser adders and lesser iterative steps. As a result of which they occupy less space as compared to the serial multiplier.......

Keywords: Multipliers, FPGA, DSP, Embedded and VHDL

[1]. Naveen Kumar, Manu Bansal, Navnish Kumar" VLSI Architecture of Pipelined Booth Wallace MAC unit" International Journal of Computer Application(0975-8887)
[2]. Fayed, Ayman A., Bayoumi, Magdy A., "A Merged Multiplier-Accumulator for high speed signal processing applications", IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), pp 3212 -3215, 2002.
[3]. Abenet Getahun "Booth Multiplication Algorithm" Fall 2003 CSCI 401. [4] Sarita Singh, Sachin Mittal"VHDL Design and implementation for optimum delay and area for Multiplier and Accumulator unit by 32 bit Sequential Multiplier" International Journal of engineering Trends and Technology Volume3 issue 5-2012
[4]. N. Honarmand, M.R.Javaheri, N.SedaghatiMokhtari and A. Afzali-Kusha "PowerEfficient Sequential Multiplication Using Pre-computation" ISCAS 2006.

ABSTRACT: The logic gates are the fundamental building blocks of VLSI and embedded applications. These gates can be designed using several design techniques and implemented at different levels of architectures. This paper focuses on design and evaluate the performance of logic gates used in the Adders and Multiplier using various design technique like CMOS design GDI design and PTL design. These different design styles have pros and corns with reference to performance measure as Delay, Power consumption, Area and Gate Count........

Keywords: Logic Gate, CMOS design, GDI design, Degenerated PTL design, CADENCE, 180nm technology, Area, Power and Delay.

[1]. A P Godse, U A Bakshi "Basic electronics- Logic gates" A introduction to basic gates and its behavior, PP 5-35 to 5-38,2015, ISBN 978-93-332-0536-8.
[2]. Neha Goyal, Renu Single, Puneet Goyal, "Study and Analysis of Universal Gate using Stacking Low Power Technique", International Journal of Computer Science and Information Technology, Vol 5 (3), 2014
[3]. Raiz Sultane, Jagannath Samantha, "Comparison of Different Design Technique of XOR and AND Gate using EDA Simulation Tool", International Journal of VLSI and Embedded System, Vol 04, Issue 03, May-June 2013
[4]. Sandeep Sangwan, Mrs Jyothi Kedia, Deepak Kedia, "A Comparative Analysis of Different CMOS Logic Design Techniques for Low Power and High Speed", International Journal of Advance Research in Electrical, Electronics and Instrumentation Engineering, Vol 2, Issue 10, October 2013
[5]. Sudeshna Sarkar,Monika Jain, Arpita Saha, Amitha Rathi, "Gate Diffusion Input: A Technique for Fast Digital Circuits (Implementation on 180 nm Technology)", IOSR Journals of VLSI and Signal Processing, Vol 4, Issue 2, Ver. IV (March-April 2014)

ABSTRACT:Full adder is the functional building block and basic component in several architectures found in VLSI and DSP applications, Adder is a versatile component and mainly used in addition and multiplication as the basic processing element; Adder in a VLSI application is used in ALU design, Address generation in processors, Multipliers and so on. In DSP applications it is used code for conversion, Signed addition and Signed multiplication, Transformations and signal processing applications. This defines the need and importance of designing an adder block in effective way........

Keywords: Full adder, Systolic Array Architectures, CADENCE Design Suite, 28Transistor CMOS full adder design,10Transistor based GDI design, Gate count, Power, Delay, and Power Delay Product.

[1] Kunjan D.shinde, Jayashree C. Nidagundi, "Design of fast and efficient 1-bit full adder and its performance Analysis", International conference on control, Instrumentation, Communication and computational technologies (ICCICCT)
[2] Preeti Verma, Ramnish Kumar, "Performance Analysis of Various Adder circuits on 180nm technology", IJECT Vol. 6, Issue 3, July - Sept 2015.
[3] Shaloo Yadav, Kavita Chauhan, "Study and Analysis of various types of Full adder's scheme for 250nm CMOS technology", International Journal of Electrical, Electronics and Computer Engineering, ISSN No. (Online): 2277-2626.
[4] Sardindu Panda, A.Banerjee, Dr. A.K Mukhopadhyay, "Power and delay comparison in between different types of Full Adder circuits", International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, Vol. 1, Issue 3, September 2012.

ABSTRACT: India is an agricultural country wherein more than 65% population is depend on agriculture. The crop loss due to diseases is approximately 10 to 30%. Farmers judge the diseases by their experience but it is not accurate and proper way. Sometimes farmers take opinion from experts to detect the diseases but this is also a time consuming way. At the time of inspection of crop damage, the inspection committee faces many problems about the identification of disease and actual percentage loss of crop due to disease........

Keywords: Image, Segmentation, Classification, feature, color, texture, disease, cotton

[1] Prof. Sanjay B. Dhaygude, Mr. Nitin P. Kumbhar, "Agricultural plant Leaf Disease Detection Using Image Processing" International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, Vol. 2, Issue 1, January 2013.
[2] Sabah Bashir, Navdeep Sharma, "Remote Area Plant Disease Detection Using Image", IOSR Journal of Electronics and Communication Engineering (IOSRJECE), ISSN : 2278-2834, Volume 2, Issue 6, Sep-Oct 2012.
[3] A. Meunkaewjinda, P. Kumsawat, K. Attakitmongcol, A. Srikaew, " Grape Leaf disease detection from color imagery using hybrid intelligent system", Proceedings of ECTI-CON 2008.
[4] P. Revathi, M. Hemalatha, "Classification of Cotton Leaf Spot Diseases Using Image Processing Edge Detection Techniques", IEEE : International Conference on Emerging Trends in Science, Engineering and Technology- 2012.
[5] Ajay A. Gurjar, Viraj A. Gulhane, "Disease Detection On Cotton Leaves by Eigenfeature Regularization and Extraction Technique", International Journal of Electronics, Communication & Soft Computing Science and Engineering, Volume 1, Issue 1.

ABSTRACT: The goal of the project is to design a high gain bandwidth op-amp to be used in a switched capacitor filter for baseband sampling in a DECT receiver [1]. DECT requires a 700KHz baseband bandwidth, which sets the anti-aliasing sampling frequency to 1.4MHz. Adding another 5X oversampling to adequately suppress higher frequency aliases, takes the sampling rate to 7MHz. Sampling at 10X the highest desired frequency should also be enough for the continuous time approximation necessary for switched capacitor filtering.

[1]. A 1.9GHz Wide-Band IF Double Conversion CMOS Integrated Receiver for Cordless Telephone Applications, Jacques C. Rudell, Jia-JiunnOu, Thomas B. Cho, George Chien, Francesco Brianti, Jeffrey A. Weldon, Paul R. Gray, IEEE International Solid State Circuits Conference, pp. 304-305, 476, February 1997
[2]. Multi Stage Amplifier Topologies with Nested Gm-C Compensation, Fan You, Sherif H. K. Embabi, Member, IEEE and Edgar Sanchez-Sinencio, Fellow, IEEE, IEEE Journal of Solid State Circuits, Vol. 32, No. 12, December 1997
[3]. Data Converters by Franco Maloberti
[4]. CMOS Analog Circuit Design by Philip E. Allen Douglas R. Holberg
[5]. Design of Analog CMOS Integrated Circuits by BehzadRazavi